Stack 'em high and Pack 'em deep - 45 nm and below

  • Posted on
  • by
intel_300mm_45nm_wafer_2.jpg

MetaRAM, a new startup recently announced new technology to produce less expensive DRAM by packing four times the number of 1 Gbit DRAM chips per module. To give some perspective, a high-end PC server with 256 Gbytes of RAM in a four-socket server can cost up to $500,000. Fred Weber, the CEO was the former CTO from Advanced Micro Devices. The cost savings by some manufacturers of 8 Gbyte DIMMs, such as Smart Modular, are significant. They expect to ship new modules using MetaRAMs chips for $1500 vs. $5000. This can cut the price of an end system by a factor of 10. An eight-way super PC server with 256 Gybtes of RAM can be had for about $50,000 vs. half a million. Why is this interesting? As you can affordably pack and dense real memory, you can run an entire enterprise database in RAM versus from a storage device. You reduce the latency and performance issues of data access between the microprocessor and the I/O device. What the processor is looking for would be held in memory. This also makes virtualization a better value proposition because you can increase the amount of virtual machines running various applications side by side within the same physical platform. This reduces power consumption, heat and maintenance from a data center perspective.  These chips are made at TSMC in their 180nm technology (huge by nm standards). Sun recently announced they picked TSMC to build the SPARC chips they design. Sun joins TI in the move away from internal fabrication of chips. Historically, this was seen as a major disadvantage as merchant semiconductor manufacturers were always one or two generations behind U.S. semiconductor companies, if we were sub-micron, they were 1 micron or more.

STEPPER.JPG

My illustrious CEO at one time, Jerry Sanders from AMD once said, "real mean have fabs." The wafer fab has long since gone offshore now along with contract manufacturing and other services. Intel's new ultramobile microprocessor are 45 nm, TI stopped advancing at 65nm. Many analysts believe the foundries can achieve large production volumes quickly by serving multiple chip designers. TMSC is down the 45nm learning curve today. The only problem is that learning insights from process technology accrue to the manufacturer, not the designer. Chip design used to be a closed-loop, fully end-to-end design process where the nano-world belonged to the designers. The transistor logic, lithography, steppers, reticles, wafers etc. all came together in a beautiful process that began with taping out the first silicon and testing the output of a once sophisticated wafer fab process. Has the wafer fab gone the way of refineries? No one wants to build one here anymore.